The present invention generally relates to the formation of vertical, shallow, and lightly doped, junctions for a vertical transistor, and more particularly to an improved method/structure that makes it possible to process a buried contact with reduced outdiffusion while still maintaining sufficient overlap between the buried contact and the transistor channel.
With further shrinking of groundrules for logic and dynamic random access memory (DRAM) devices, development of improvements becomes necessary. In case of planar logic and DRAM devices, short channel effects limit device performance. For DRAMs with vertical access transistor, the buried contact outdiffusion has to be reduced for isolation reasons, but connectivity to the select transistor must be assured. The invention described below processes a shallow buried contact by reducing the outdiffusion without degrading the connectivity to the select transistor